1. Field of the Invention
The present invention relates to a semiconductor storage device and a manufacturing method thereof.
2. Related Background Art
Various proposals have been submitted to realize a single electron memory that can operate at room temperature. The single electron memory is a memory that utilizes a Coulomb blockade phenomenon observed in a quantum dot, and a fundamental principle thereof is summarized in U.S. Pat. No. 6,323,504. A single electron memory element with silicon crystal grains having a diameter of 6 nm is proposed in, e.g., Japanese Laid open (kokai) No. 2004-343128.
However, for the single electron memory element proposed in Japanese laid open (kokai) No. 2004-343128, stable mass production thereof is difficult due to the difficulty in controlling the size of such micro crystal grains.
Further, in U.S. Pat. No. 6,894,352B2 is proposed a single electron transistor that is operable on a trial production stage with each quantum dot of 80 nm or below being confined to an electric field. However, in U.S. Pat. No. 6,894,352B2, manufacture must be carried out by using EB (Electron Beam) lithography, and hence there is a drawback that mass production is difficult.
PROCEEDINGS OF THE IEEE Vol. 87 No. 4, April 1999 (which will be referred to as a “Non-patent document 1” hereinafter) discloses the world's first single electron memory that operates at room temperature, and spontaneous formation of an extra fine current path or a charge storage region which is as large as a crystal grain is realized by utilizing irregularities of a polysilicon film.
However, the element disclosed in Non-patent document 1 is not only insufficient in controllability over processes but also has a drawback that peripheral circuits have a large scale. For example, a variation compensating circuit is required.
In 2005 IEEE International Electron Device Meeting (2005 IEDM), Lecture No. 19.4 (which will be referred to as a “Non-patent document 2” hereinafter) is proposed a memory cell having a two-dimensional structure achieved by aligning thin lines vertically and horizontally and providing four gates. However, the element disclosed in Non-patent document 2 likewise has a drawback that mass production is difficult since EB exposure is required.